DocumentCode
396555
Title
A massively scaleable decoder architecture for low-density parity-check codes
Author
Selvarathinam, Anand ; Choi, Gwan ; Narayanan, Krishna ; Prabhakar, Abhiram ; Kim, Euncheol
Author_Institution
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
Volume
2
fYear
2003
fDate
25-28 May 2003
Abstract
A massively scalable architecture for decoding low-density parity-check codes is presented in this paper. This novel architecture uses hardware scaling and memory partitioning to achieve a throughput of 100 Gbps. Simulation results show that this throughput is achieved without significant bit-error performance degradation.
Keywords
decoding; error statistics; parallel architectures; parity check codes; 100 Gbit/s; bit error rate; hardware scaling; low-density parity-check code; massively scaleable decoder architecture; memory partitioning; parallel architecture; AWGN; Availability; Bit error rate; Degradation; Delay; Hardware; Iterative decoding; Parallel architectures; Parity check codes; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN
0-7803-7761-3
Type
conf
DOI
10.1109/ISCAS.2003.1205887
Filename
1205887
Link To Document