A low-power, memoryless direct digital frequency synthesizer architecture

Author

Palomäki, K.I. ; Nittylahti, J.

Author_Institution

Digital & Comput. Syst. Lab., Tampere Univ. of Technol., Finland

Volume

2

fYear

2003

fDate

25-28 May 2003

Abstract

In this paper, a compact, low-power, memoryless direct digital frequency synthesizer architecture based on Taylor series approximation is presented. For improved performance, two reference points are applied to the sine and cosine approximation. The advantages of using two reference points include low power consumption, small design area and improved approximation accuracy. Also, a design example outperforming the area and power consumption of the traditional look-up table approach by 10% is presented. The design size is 10,282 transistors and the average power consumption 8.8 mW at 30 MHz system clock.

Keywords

CMOS digital integrated circuits; direct digital synthesis; integrated circuit design; low-power electronics; series (mathematics); 30 MHz; 8.8 mW; CMOS technology; Taylor series approximation; approximation accuracy; cosine approximation; design size; low power consumption; low-power memoryless direct digital frequency synthesizer architecture; reference points; sine approximation; small design area; Clocks; Computer architecture; Counting circuits; Energy consumption; Frequency synthesizers; Laboratories; Pipeline processing; Signal synthesis; Table lookup; Taylor series;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205893

Filename

1205893