DocumentCode
396582
Title
Clock recovery circuit with adiabatic technology (quasi-static CMOS logic)
Author
Yeung, W.K. ; Chan, Cheong-Fat ; Choy, Chiu-Sing ; Pun, Kong-Pang
Author_Institution
Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin, China
Volume
2
fYear
2003
fDate
25-28 May 2003
Abstract
This paper presents a novel approach of using digital adiabatic circuit to perform clock-recovery for an amplitude-shift-key (ASK) transmission system. The adiabatic clock recovery consists of only 39 stages of AqsCMOS inverter and consumes 106 μW. The circuit is specially designed for low power contactless smart card using adiabatic logic.
Keywords
CMOS logic circuits; amplitude shift keying; logic gates; low-power electronics; smart cards; synchronisation; 106 muW; AqsCMOS inverter; adiabatic technology; amplitude-shift-key transmission; clock recovery circuit; low power contactless smart card; quasi-static CMOS logic; Amplitude shift keying; CMOS logic circuits; CMOS technology; Clocks; Diodes; Inverters; Power supplies; Signal generators; Smart cards; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN
0-7803-7761-3
Type
conf
DOI
10.1109/ISCAS.2003.1205928
Filename
1205928
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