Quadrature direct digital frequency synthesizers: area-optimized design map for LUT-based FPGAs

Author

Cardells-Tormo, Francisco ; Valls-Coquillat, Javier

Author_Institution

R&D, Hewlett-Packard Co., Sant Cugat Del Valles, Spain

Volume

2

fYear

2003

fDate

25-28 May 2003

Abstract

This paper deals with the FPGA-implementation of quadrature direct digital frequency synthesizers (QDDFS), and in particular with those based on CORDIC, interpolation and memory compression. We provide results of maximum throughput, i.e. 302 MHz, when mapping QDDFS architectures on current LUT-based field-programmable technology. We take into account those VLSI design guidelines that work well on FPGAs and architectural considerations to design efficient (in terms of area and throughput) QDDFS, up to 56% faster than commercial cores. Finally, we present a design map that combines the phase-to-amplitude techniques reviewed in this article so as to minimize the overall area.

Keywords

VLSI; circuit optimisation; digital arithmetic; direct digital synthesis; field programmable gate arrays; interpolation; logic design; 100 MHz; 302 MHz; CORDIC; IF processing; LUT-based FPGA; QDDFS maximum throughput; VLSI design guidelines; area optimization; interpolation; memory compression; phase-to-amplitude techniques; quadrature direct digital frequency synthesizers; Clocks; Computer architecture; Field programmable gate arrays; Frequency synthesizers; Guidelines; Logic circuits; Logic design; Logic devices; Reconfigurable logic; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205955

Filename

1205955