Title :
FPGA implementation of block truncation coding algorithm for gray scale images
Author :
Saif, S.M. ; Abbas, Hazem M. ; Nassar, Salwa M.
Author_Institution :
Electron. Res. Inst., Giza, Egypt
Abstract :
This paper presents a Field Programmable Gate Array (FPGA) implementation for video compression using a Block Truncation Coding (BTC) image compression technique. The implementation exploits the inherent parallelism of the BTC algorithm to provide efficient algorithm-to-architecture mapping. The Xilinx VirtexE BTC implementation has shown to provide 20.5 × 106 of pixels per second, which is about 3000 times faster than an Intel Pentium III 550 MHz processor.
Keywords :
block codes; field programmable gate arrays; parallel algorithms; quantisation (signal); video coding; FPGA implementation; Xilinx VirtexE BTC implementation; algorithm-to-architecture mapping; block truncation coding algorithm; block truncation coding image compression technique; gray scale images; inherent parallelism; video compression; Data compression; Field programmable gate arrays; Hardware; Image coding; Image processing; Image storage; Microprocessors; Pixel; Quantization; Video compression;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1206006
