Towards a general framework for an FPGA-based FFT coprocessor

There have been a large number of fast Fourier transform (FFT) algorithms which have been developed over the years. Among these algorithms, the most promising are the Radix-2, Radix-4, Split-Radix and fast Hartley transform (FHT). In this paper we present an investigation into the design and implementation of the above mentioned FFT algorithms using Handel-C - a recently developed C-like programming language for compilation of high-level programs directly into FPGA hardware. The algorithms have been implemented and verified on the Celocixa RC1000 FPGA development board. A detailed evaluation has also been reported based on maximum system frequency, chip area and computation time.