Creating a reusable testbench using cadence´s testbuilder and AMBA TVM

This paper presents a system-level verification methodology to validate complex digital intellectual property (IP) blocks. This methodology, called transaction-based verification (TBV), abstracts operations over a design-under-verification (DUV) interface from the pin-level to the transaction-level, separating the details of the interface from the generation and monitoring of data on those interfaces. This methodology is illustrated by a tutorial delivered as part of the Canadian system-on-chip research network (SOCRN) infrastructure.