• DocumentCode
    397179
  • Title

    Syntax code analysis and generation for Verilog

  • Author

    Zaki, Mohamed ; Tahar, Sofiène

  • Author_Institution
    Dept. of ECE, Concordia Univ., Montreal, Que., Canada
  • Volume
    1
  • fYear
    2003
  • fDate
    4-7 May 2003
  • Firstpage
    235
  • Abstract
    In this paper, we present a syntax analyser tool for Verilog programs which can be used as a front end to debugging and program verification tools.
  • Keywords
    computational linguistics; hardware description languages; program debugging; program diagnostics; program verification; Verilog programs; debugging tool; program verification tool; syntax analyser tool; syntax code analysis; syntax code generation; Automatic control; Circuit testing; Costs; Data analysis; Data mining; Debugging; Flow graphs; Hardware design languages; Information analysis; Phase detection;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical and Computer Engineering, 2003. IEEE CCECE 2003. Canadian Conference on
  • ISSN
    0840-7789
  • Print_ISBN
    0-7803-7781-8
  • Type

    conf

  • DOI
    10.1109/CCECE.2003.1226386
  • Filename
    1226386
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=397179