• DocumentCode
    399565
  • Title

    ATE-amenable test data compression with no cyclic scan registers

  • Author

    Hashempour, Hamidreza ; Lombardi, Fabrizio

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
  • fYear
    2003
  • fDate
    3-5 Nov. 2003
  • Firstpage
    151
  • Lastpage
    158
  • Abstract
    This paper deals with a novel data compression technique for automatic test equipment (ATE). A new correlation extraction technique is presented which allows spanning of the compressed test data over the memory of multiple ATE channels. After reordering, vector processing is executed on a columnwise basis such that bits in the same position of all vectors are simultaneously provided to each pin of the head. Differentiation which is commonly used to extract correlation among vectors is not required in the proposed technique. Several ATE issues related to memory utilization, off-chip compression/decompression, decompression circuitry area overhead (inclusive of the area of the cyclic-scan-register, CSR), and entropy of test data (as figure of merit for correlation extraction) are analyzed. Experimental results for combinational and sequential benchmark circuits are presented to substantiate the validity of the proposed technique for an ATE environment.
  • Keywords
    automatic test equipment; combinational circuits; correlation methods; data compression; integrated circuit testing; logic testing; sequential circuits; ATE environment; ATE-amenable test data compression; automatic test equipment; columnwise vector processing; combinational benchmark circuits; compressed test data spanning; correlation extraction figure of merit; correlation extraction technique; cyclic scan registers; data compression technique; data reordering; decompression circuitry area overhead; differentiation; memory utilization; multiple ATE channel memory; off-chip compression; off-chip decompression; sequential benchmark circuits; test data entropy; Application specific integrated circuits; Circuit testing; Data compression; Data mining; Hardware; Integrated circuit testing; Manufacturing; Registers; Test data compression; Workstations;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI Systems, 2003. Proceedings. 18th IEEE International Symposium on
  • ISSN
    1550-5774
  • Print_ISBN
    0-7695-2042-1
  • Type

    conf

  • DOI
    10.1109/DFTVS.2003.1250107
  • Filename
    1250107