Communication centric architectures for turbo-decoding on embedded multiprocessors

Software implementations of channel decoding algorithms are attractive for communication systems with their large variety of existing and emerging standards due to their flexibility and extensibility. For high throughput, however, a single processor can not provide the necessary computing power. Using several processors in parallel, without exploiting the internal parallelism of the algorithm, leads to intolerable overhead in area, power consumption, and latency. We propose a multiprocessor based turbo-decoder implementation where inherently parallel decoding tasks are mapped onto individual processing nodes. The implied challenging inter-processor communication is efficiently handled by our framework such that throughput is not degraded. In this paper, we present communication centric architectures from buses to heterogenous networks that allow us to interconnect numerous processors to perform high throughput turbo-decoding.