DocumentCode
400467
Title
HiBRID-SoC: a multi-core system-on-chip architecture for multimedia signal processing applications
Author
Stolberg, Hans-Joachim ; Berekovic, Mladen ; Friebe, Lars ; Moch, Sören ; Flügel, Sebastian ; Mao, Xun ; Kulaczewski, Mark B. ; Klussmann, H. ; Pirsch, Peter
Author_Institution
Inst. fur Mikroelektronische Syst., Hannover Univ., Germany
fYear
2003
fDate
2003
Firstpage
8
Abstract
The HiBRID-SoC multi-core system-on-chip targets a wide range of application fields with particularly high processing demands, including general signal processing applications, video and audio de-/encoding, and a combination of these tasks. For this purpose, the HiBRID-SoC integrates three fully programmable processors cores and various interfaces onto a single chip, all tied to a 64 bit AMBA AHB bus. The processor cores are individually optimized to the particular computational characteristics of different application fields, complementing each other to deliver high performance levels with high flexibility at reduced system cost. The HiBRID-SoC is fabricated in a 0.18 μm 6LM standard-cell CMOS technology, occupies about 82 mm2, and operates at 145 MHz.
Keywords
CMOS integrated circuits; audio coding; digital signal processing chips; integrated circuit design; multimedia computing; system buses; system-on-chip; video coding; 0.18 micron; 145 MHz; 64 bit; CMOS; HiBRID-SoC; audio coding; audio decoding; interfaces; multi-core system-on-chip architecture; multimedia signal processing applications; programmable processors cores; system bus; video coding; video decoding; Application software; Computer architecture; MPEG 4 Standard; Multimedia systems; Signal processing; Signal processing algorithms; System-on-a-chip; Testing; Video coding; Video signal processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition, 2003
ISSN
1530-1591
Print_ISBN
0-7695-1870-2
Type
conf
DOI
10.1109/DATE.2003.1253797
Filename
1253797
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