Clock scheduling and clocktree construction for high performance ASICs

In this paper we present a new method for clock scheduling and clocktree construction that improves the performance of high-end ASICs significantly. First, we compute a clock schedule that yields the optimum cycle time and the best possible clock distribution with respect to early and late mode; in particular the number of critical tests is minimized. Second, individual arrival time intervals are computed for all endpoints of the clocktree. Finally, we construct a clocktree that realizes arrival times within these intervals and exploits positive slacks to save power consumption. We demonstrate the superiority of our method to previous approaches by experimental results on industrial ASICs with up to 194000 registers and more than 160 clock domains. We improved the clock frequencies by 5-28% up to 1.033 GHz (in hardware).