Title :
An enhanced 100nm CMOS logic technology with germanium preamorphized PMOS
Author :
Chan, S.T.H. ; Benistant, F. ; Al-Bayati, A.
Abstract :
80nm physical gate length CMOS technology using germanium preamorphization implantation (Ge PAI) has been developed. With optimum Ge PAI conditions, PMOS device performance enhancement can be achieved through improved dopant activation at S/D extension region while short channel effects are also reduced. It is also shown, for the first time, that Ge PAI at S/D junction can also achieve performance enhancement depending on device architecture.
Keywords :
CMOS integrated circuits; CMOS logic circuits; germanium; ion implantation; semiconductor doping; 100 nm; 80 nm; Ge preamorphized PMOS; Si:Ge; device architecture; enhanced 100nm CMOS logic technology; preamorphization implantation; Annealing; Boron; CMOS logic circuits; CMOS technology; Capacitance; Germanium; Implants; MOS devices; Semiconductor device manufacture; Semiconductor materials;
Conference_Titel :
Ion Implantation Technology. 2002. Proceedings of the 14th International Conference on
Conference_Location :
Taos, New Mexico, USA
Print_ISBN :
0-7803-7155-0
DOI :
10.1109/IIT.2002.1257940
