Fast Approximation Framework for Timing and Power Analysis of Ultra-Low-Voltage Circuits

Ultra-low-voltage operation can greatly reduce the power consumption of circuits. However, there is no fast, effective, and comprehensive technique for designers to estimate power, delay, or effects of process variation of a design operating in the ultra-low-voltage region. This paper presents a simulation framework that can quickly and accurately characterize a circuit from nominal voltage to the subthreshold region. The framework uses the nominal frequency and power of a target circuit, obtained using gate-level or transistor-level simulation tools, and normalized ring oscillator curves to predict delay and power characteristics at lower operating voltages. Specific contributions of this article include a weighted average method, an improvement to a previously published form of this framework, as well as a methodology to estimate the effects of process variation based on the same framework. The weighted averages framework takes into account the types of gates that are used in the circuit and critical path to give a more accurate power and timing characterization. Despite the varying results by several orders of magnitude, the errors are no greater than 20.01%, 15.30%, and 8.870% for circuit delay, active energy, and leakage power, respectively, for the weighted averages technique. To validate the framework, a detailed analysis is given in the presence of a variety of design parameters as well as a range of benchmark circuits.