A low voltage, low noise CMOS RF receiver front-end

Author

Long, Jie ; Weber, Robert J.

Author_Institution

Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA

fYear

2004

fDate

2004

Firstpage

393

Lastpage

397

Abstract

This paper presents a low-power, low-voltage radio frequency (RF) receiver front-end implemented in a 0.18 μm CMOS process that is intended for 2.4 GHz wireless applications. It includes a single-ended low-noise amplifier (LNA) with on-chip spiral inductors and a passive switching direct downconversion mixer. The LNA has a simulated noise figure of 0.75 dB and power gain of 12.9 dB. With a -30 dBm RF input and a 0.45V LO signal, the mixer has a simulated noise figure of 7.8 dB, conversion gain of -2.2 dB, 1-dB compression point of -8 dBm, input third-order intercept point (IIP3) of 14.4 dBm. Comparison between this work and others have shown better noise performance and less power dissipation.

Keywords

CMOS integrated circuits; amplifiers; inductors; integrated circuit modelling; integrated circuit noise; radio receivers; system-on-chip; -2.2 dB; 0.18 micron; 0.45 V; 0.75 dB; 1 dB; 12.9 dB; 2.4 GHz; CMOS process; LNA; conversion gain; low noise CMOS RF receiver front end; low voltage CMOS RF receiver front end; noise figure; noise performance; on-chip spiral inductors; passive switching direct downconversion mixer; power dissipation; power gain; single ended low noise amplifier; wireless applications; CMOS process; Gain; Inductors; Low voltage; Low-noise amplifiers; Mixers; Noise figure; Radio frequency; Receivers; Spirals;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2004. Proceedings. 17th International Conference on

Print_ISBN

0-7695-2072-3

Type

conf

DOI

10.1109/ICVD.2004.1260954

Filename

1260954