An area-efficient router for the Data-Intensive Architecture (DIVA) system

Author

Mediratta, Sumit ; Sondeen, Jeff ; Draper, Jeffrey

Author_Institution

Inf. Sci. Inst., Univ. of Southern California, Marina del Rey, CA, USA

fYear

2004

fDate

2004

Firstpage

863

Lastpage

868

Abstract

A key component of the Data-Intensive Architecture (DIVA) is the Processing-In-Memory (PIM) Routing Component (PiRC) that is responsible for efficient communication between PIM chips. This paper presents the design of a low area, delay and power router for DIVA. A 58.5% saving in area and 86% reduction in load on the clock as compared to an earlier PIM router design makes the presented design ideal for use in the second version of DIVA, with low area being a critical design requirement for DIVA. This paper also gives a comparison of the presented design with an earlier PIM router design in terms of delay and power to justify the new design choice.

Keywords

SRAM chips; coprocessors; memory architecture; network routing; parallel architectures; performance evaluation; SRAM chips; coprocessors; data intensive architecture system; network routing; performance evaluation; processing in-memory chips; processing in-memory routing component; static random access storage; Character generation; Clocks; Communication system control; Coprocessors; Delay; Flip-flops; Multiprocessor interconnection networks; Random access memory; Routing; Yarn;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2004. Proceedings. 17th International Conference on

Print_ISBN

0-7695-2072-3

Type

conf

DOI

10.1109/ICVD.2004.1261039

Filename

1261039