• DocumentCode
    402663
  • Title

    A cache coherence scheme suitable for massively parallel processors

  • Author

    Baldwin, Reid

  • Author_Institution
    Dept. of Comput. Sci., Michigan State Univ., MI, USA
  • fYear
    1993
  • fDate
    15-19 Nov. 1993
  • Firstpage
    730
  • Lastpage
    739
  • Abstract
    A new approach to cache coherent networks is proposed and analzyed. This approach is highly scalable, so it is appropriate for massively parallel multiprocessors. The network switches of a MIN are enhanced such that they are capable of handling the majority of the cache coherence burden. The latency for both reads and writes is O(log N) independent of the number of copies. The memory overhead of this approach is O(C log2 N).
  • Keywords
    cache storage; computational complexity; multiprocessor interconnection networks; parallel processing; MIN; cache coherence burden; cache coherence scheme; cache coherent networks; highly scalable approach; latency; massively parallel multiprocessors; massively parallel processors; memory overhead; network switches; Broadcasting; Computer science; Monitoring; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Supercomputing '93. Proceedings
  • ISSN
    1063-9535
  • Print_ISBN
    0-8186-4340-4
  • Type

    conf

  • DOI
    10.1109/SUPERC.1993.1263527
  • Filename
    1263527
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=402663