DocumentCode
403565
Title
SoC test scheduling with power-time tradeoff and hot spot avoidance
Author
Chin, James ; Nourani, Mehrdad
Author_Institution
Center for Integrated Circuits & Syst., Texas Univ., Richardson, TX, USA
Volume
1
fYear
2004
fDate
16-20 Feb. 2004
Firstpage
710
Abstract
We present a test scheduling methodology for core-based system-on-chips that can avoid hot spots and allows tradeoff between physical power dissipation and overall test time. A mixed integer linear programming formulation is presented to globally perform the power-time tradeoff, satisfy constraints, and produce the SoC test schedule.
Keywords
integer programming; integrated circuit testing; linear programming; scheduling; system-on-chip; SoC test; core-based system-on-chips; hot spot avoidance; integer programming; linear programming; physical power dissipation; power-time tradeoff; test scheduling; test time; Circuit testing; Energy consumption; Integrated circuit testing; Mixed integer linear programming; Performance evaluation; Power dissipation; Power distribution; Scheduling algorithm; System testing; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
ISSN
1530-1591
Print_ISBN
0-7695-2085-5
Type
conf
DOI
10.1109/DATE.2004.1268942
Filename
1268942
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