Sizing and characterization of leakage-control cells for layout-aware distributed power-gating

This paper proposes a methodology for sleep transistor sizing for usage in a novel, single-threshold leakage cut-off approach, where power gating cells are distributed row-by-row in a fully placed circuit. Sizing equations are obtained by performing SPICE simulations for a 130nm technology. Furthermore, the layout of a test case is considered and power and delay values are extracted in order to demonstrate the practical impact of our solution.