DocumentCode
403605
Title
Architecture-level performance estimation for IP-based embedded systems
Author
Ueda, Kyoko ; Sakanushi, Keishi ; Takeuchi, Yoshinori ; Imai, Masaharu
Author_Institution
Graduate Sch. of Inf. Sci. & Technol., Osaka Univ., Japan
Volume
2
fYear
2004
fDate
16-20 Feb. 2004
Firstpage
1002
Abstract
In this paper, we propose a architecture-level performance estimation method for IP-based embedded systems using system-level profiling. Our method enables the performance estimation by the following procedures: 1) System-level profiling. 2) Automatic construction of the execution dependency graph (EDG) from the profile information. 3) Estimation of the system performance based on the EDG analysis. Our method enables fast performance estimation because it can estimate the performance of various architectures from the same system-level profile information. Experimental results show that our estimation method is about 10,000 times faster than the architecture-level simulations.
Keywords
embedded systems; industrial property; performance evaluation; architecture level performance estimation; architecture level simulation; embedded systems; execution dependency graph; intellectual property; profile information; system level profiling; Data processing; Design methodology; Embedded system; Information analysis; Information science; Multimedia systems; Performance analysis; System performance; Timing; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
ISSN
1530-1591
Print_ISBN
0-7695-2085-5
Type
conf
DOI
10.1109/DATE.2004.1269024
Filename
1269024
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