DocumentCode
403655
Title
A macromodelling methodology for efficient high-level simulation of substrate noise generation
Author
Elvira, Luis ; Martorell, Ferran ; Aragonés, Xavier ; González, José Luis
Author_Institution
Electron. Eng. Dept., Univ. Politecnica de Catalunya, Barcelona, Spain
Volume
2
fYear
2004
fDate
16-20 Feb. 2004
Firstpage
1362
Abstract
Efficient prediction of the substrate noise generated by digital sections is currently a major challenge in system-on-a-chip design. In this paper a macromodel to accurately and efficiently predict the substrate noise generated by digital standard cells is presented. The macromodel accuracy is demonstrated for some simple circuits.
Keywords
cellular arrays; circuit simulation; integrated circuit modelling; integrated circuit noise; substrates; system-on-chip; SOC; digital standard cells; high level simulation; macromodelling; substrate noise generation; system-on-chip design; Capacitance; Circuit noise; Circuit simulation; Discrete event simulation; Equivalent circuits; Integrated circuit noise; Noise generators; Noise level; Performance analysis; Software libraries;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
ISSN
1530-1591
Print_ISBN
0-7695-2085-5
Type
conf
DOI
10.1109/DATE.2004.1269089
Filename
1269089
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