DocumentCode
403661
Title
Dynamic voltage and cache reconfiguration for low power
Author
Nacul, Andre C. ; Givargis, Tony
Author_Institution
California Univ., Irvine, CA, USA
Volume
2
fYear
2004
fDate
16-20 Feb. 2004
Firstpage
1376
Abstract
This article deals about dynamic voltage and cache reconfiguration online algorithm that dynamically adapts the processor speed and the cache subsystem to the workload requirements for the purpose of saving energy. The workload is considered to be a set of tasks with real-time deadlines. Our online algorithm is invoked as part of the OS scheduler, which performs standard earliest deadline first(EDF)task scheduling first. Then, our online algorithm, determines an ideal voltage/cache configuration for the current executing task.
Keywords
Pareto optimisation; cache storage; low-power electronics; power consumption; Pareto optimisation; cache subsystem; dynamic cache reconfiguration online algorithm; dynamic voltage scaling; power consumption; processor speed; real time deadlines; standard earliest deadline; Dynamic voltage scaling; Embedded system; Frequency; Heuristic algorithms; Potential energy; Processor scheduling; Scheduling algorithm; Timing; Voltage control; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
ISSN
1530-1591
Print_ISBN
0-7695-2085-5
Type
conf
DOI
10.1109/DATE.2004.1269096
Filename
1269096
Link To Document