A demonstration of co-design and co-verification in a synchronous language

Author

Singh, Satnam

Author_Institution

Xilinx Inc., San Jose, CA, USA

Volume

2

fYear

2004

fDate

16-20 Feb. 2004

Firstpage

1394

Abstract

This paper illustrates how the synchronous programming language Esterel [3] can be used to design and verify both hardware and software. Also illustrates that power of combining these two complementary technologies for the design and verification of embedded systems. Finally we show how the Esterel technique fits into a conventional system level design flow based on Xilinx´s Virtex-II PRO FPGA and present several case studies and actual demonstration of a complete system from concept to implementation.

Keywords

embedded systems; field programmable gate arrays; formal verification; hardware-software codesign; programming languages; Esterel technique; FPGA; Xilinx; co-verification; embedded system design; embedded system verification; field programmable gate array; hardware-software codesign; synchronous programming language; system level design; Control systems; Embedded software; Field programmable gate arrays; Hardware; Logic programming; Portable computers; Power system modeling; Software safety; Space exploration; System-level design;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings

ISSN

1530-1591

Print_ISBN

0-7695-2085-5

Type

conf

DOI

10.1109/DATE.2004.1269104

Filename

1269104