A novel polysilicon gate engineering by laser thermal process for high performance sub-40 nm CMOS devices

Author

Yamamoto, T. ; Okabe, K. ; Kubo, T. ; Goto, K. ; Morioka, H. ; Wang, Y. ; Lin, T. ; Talwar, S. ; Kase, M. ; Sugii, T.

Author_Institution

Fujitsu Ltd., Tokyo, Japan

fYear

2003

fDate

10-12 Dec. 2003

Firstpage

424

Lastpage

425

Abstract

A novel polysilicon gate engineering by laser thermal process (LPT) is developed to minimize the gate depletion even under low temperature SD-RTA and applied to sub-40 nm CMOS devices. BEOL process is optimized to suppress dopant deactivation. SD-RTA technique is developed to supress dopant dose loss for the maximization of the merit of LTP.

Keywords

MOSFET; elemental semiconductors; laser beam annealing; silicon; 40 nm; BEOL process; CMOS devices; RTA process; Si; back end of line process; complementary metal oxide semiconductor; dopant deactivation; dopant dose loss; gate depletion; laser thermal process; polysilicon gate engineering; rapid thermal annealing; Annealing; CMOS process; CMOS technology; MOS devices; MOSFETs; Optical device fabrication; Oxidation; Temperature control; Thermal degradation; Thermal engineering;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Device Research Symposium, 2003 International

Print_ISBN

0-7803-8139-4

Type

conf

DOI

10.1109/ISDRS.2003.1272164

Filename

1272164

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=404169