Path-based timing optimization by buffer insertion with accurate delay model

With progress in VLSI sub-micron technology, interconnect delay has become a dominant factor in chip timing, and interconnect optimization has become a critical step in the high performance design of VLSI. In this paper, an algorithm of path-based timing optimization by buffer insertion is presented. The algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look-up table for gate delay estimation. And heuristic method of buffer insertion is presented to reduce delay. The algorithm is tested by industrial circuit case. Experimental results show that our algorithm can optimize the timing of circuit efficiently and the timing constraint is satisfied.