Local logic substitution algorithm for post-layout re-synthesis

As the interconnect delay has become the most dominant factor of circuit performances, logic synthesis results without considering interconnect delay tend to lead to unsatisfactory circuit performance. In this paper, a post-layout re-synthesis scheme is proposed to tackle such a problem. In this algorithm, a local logic substitution scheme based on Alternative Logic Equivalent Block (ALEB) is used. Using the interconnect delay information provided by placement, this algorithm improves the circuit delay by substitutions of local logic blocks located on critical paths, followed by an incremental placement, is applied upon those altered blocks. The experimental results show that the algorithm reduces nearly 30% of the critical path delay without causing much area overhead.