Hardware/Software co-verification platform for EOS design

Author

Peng Wang ; Jinsong Liu ; Lieguang Zeng

Author_Institution

Dept. of Electron. Eng., Tsinghua Univ., Beijing, China

Volume

1

fYear

2003

fDate

21-24 Oct. 2003

Firstpage

195

Abstract

Ethernet over SDH/SONET (EOS) has become a hotspot in data transmission technology for it combines the merits of both Ethernet and SDH/SONET. However, implementing an EOS system on a chip is complex and needs full verifications. This paper introduces our design of Hardware/Software co-verification platform for EOS design. The hardware platform contains a microprocessor board and an FPGA (Field Programmable Gate Array)-based verification board, and the corresponding software includes test benches running in FPGAs, controlling programs for the microprocessor and a console program with GUI (Graphical User Interface) interface for configuration, management and supervision. The design is cost-effective and has been successfully employed in verifying several IP (Intellectual Property) blocks of our EOS chip. Moreover, it is flexible and can be applied as a general-purpose verification platform.

Keywords

SONET; field programmable gate arrays; graphical user interfaces; local area networks; microprocessor chips; synchronous digital hierarchy; system-on-chip; EOS design; FPGA; GUI; console program; controlling programs; data transmission technology; ethernet over SDH/SONET; field programmable gate array; graphical user interface; hardware co-verification platform; intellectual property; microprocessor board; software co-verification platform; synchronous digital hierarchy; synchronous optical network; system-on-chip; test benches; verification platform;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2003. Proceedings. 5th International Conference on

ISSN

1523-553X

Print_ISBN

0-7803-7889-X

Type

conf

DOI

10.1109/ICASIC.2003.1277522

Filename

1277522