Title :
A synchronizing method for designing VLSI chip´s P/G topology with noise and reliability considerations
Author :
Jing Li ; Chunhui Li ; Juebang Yu
Author_Institution :
Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Abstract :
The reliability and optimum result of P/G nets routing method can affect area optimization and electricity performance of whole CMOS chip. Based on the analysis of noise uniform distribution and reliability of module operation, in this paper, we present a synchronizing method for optimum design of power and ground topology. Experimental results demonstrate the better characteristic of noise uniform distribution and operating reliability.
Keywords :
CMOS integrated circuits; VLSI; circuit optimisation; integrated circuit design; integrated circuit noise; integrated circuit reliability; network routing; network topology; CMOS chip; P/G nets routing method; VLSI chip P/G topology design; area optimization; electricity performance; noise; power and ground topology design; reliability; synchronizing method; uniform distribution;
Conference_Titel :
ASIC, 2003. Proceedings. 5th International Conference on
Print_ISBN :
0-7803-7889-X
DOI :
10.1109/ICASIC.2003.1277537
