DocumentCode
405805
Title
An incremental floorplanner based on genetic algorithm
Author
Yongpan Liu ; Huazhong Yang ; Rong Luo
Author_Institution
Dept. of Electron. Eng., Tsinghua Univ., Beijing, China
Volume
1
fYear
2003
fDate
21-24 Oct. 2003
Firstpage
331
Abstract
To support incremental changes on the existing floorplan is becoming an increasingly important problem in order to cope with the complexity of the merging of VLSI design phases. An incremental floorplan algorithm based on genetic algorithms is presented in this paper. It supports incremental changes on the existing floorplan solution. Our experiments show that given an initial floorplan and incremental changes, a comparable new floorplan solution in quality can be generated with a magnitude of speedup.
Keywords
VLSI; circuit layout; genetic algorithms; integrated circuit design; VLSI design phases; floorplan solution; genetic algorithm; incremental floorplanner;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2003. Proceedings. 5th International Conference on
ISSN
1523-553X
Print_ISBN
0-7803-7889-X
Type
conf
DOI
10.1109/ICASIC.2003.1277555
Filename
1277555
Link To Document