A 1.8-V 64-kb four-way set-associative CMOS cache memory using fast sense amplifier and split dynamic tag comparators

Author

Sun Hui ; Guo Jing ; Zhang Qianling

Author_Institution

ASIC, Fudan Univ., Shanghai, China

Volume

1

fYear

2003

fDate

21-24 Oct. 2003

Firstpage

474

Abstract

This paper reports a 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18 μm 1.8 V 1P6M logic CMOS technology. This cache is designed for a 32-b RISC microprocessor. Effective latency of 3.4 ns and power consumption of 190 mW at 263 MHz are obtained at a supply voltage of 1.8 V. This performance is achieved by using high speed circuit design techniques such as modified high speed current-mode sense amplifier and split dynamic tag comparators.

Keywords

CMOS logic circuits; CMOS memory circuits; amplifiers; cache storage; comparators (circuits); content-addressable storage; current-mode circuits; power consumption; 0.18 micron; 1.8 V; 190 mW; 263 MHz; 3.4 ns; 32 byte; 64 kbyte; RISC microprocessor; complementary metal oxide semiconductor; four way set associative CMOS cache memory; high speed circuit design techniques; high speed current mode sense amplifier; logic CMOS technology; power consumption; reduced instruction set computing microprocessor; split dynamic tag comparators;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2003. Proceedings. 5th International Conference on

ISSN

1523-553X

Print_ISBN

0-7803-7889-X

Type

conf

DOI

10.1109/ICASIC.2003.1277589

Filename

1277589