• DocumentCode
    4060
  • Title

    Morphing Bus: A New Paradigm in Peripheral Interconnect Bus

  • Author

    Yanzhe Cui ; Voyles, Richard M. ; Nawrocki, Robert A. ; Guangying Jiang

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Denver, Denver, CO, USA
  • Volume
    4
  • Issue
    2
  • fYear
    2014
  • fDate
    Feb. 2014
  • Firstpage
    341
  • Lastpage
    351
  • Abstract
    Modern digital peripheral interconnect buses are typically described as one of the two types, serial or parallel, based on whether or not the physical data channel(s) is (are) shared across the bits of a coherent data word. Conventional serial and parallel buses operate in a time-multiplexed mode, allowing access to only one peripheral device at a time. PCIexpress expanded this simple bifurcation by combining serial data channels with simultaneous access to multiple peripheral devices (or multiple regions of the same peripheral). Moving to that nontime-multiplexed mode opened a new dimension by which bus architectures could be classified. Under this taxonomy of serial versus parallel and time-multiplexed versus nontime multiplexed, our Morphing Bus presents a new paradigm that fills the parallel, nontime multiplexed interconnect niche. Furthermore, the Morphing Bus eliminates the notion of an intermediate data format and thereby obviates the need for bus interface circuitry. Instead of a common data format to which all the sensors and actuators are translated, the Morphing Bus transforms-or morphs-its signal lines to meet the needs of the connected sensors or actuators. For digital sensors and actuators, this morphing is achieved through a field-programmable gate array on the processor side of the bus. As programmable devices begin to incorporate analog signal paths, the Morphing Bus paves the way for integrating analog and digital signals into a single bus paradigm. The efficacy of the Morphing Bus is verified via implementation on a miniature robot and the bandwidth of the bus implementation is experimentally characterized. Its unique physical I/O stack in the form of a helical structure provides efficient cooling and power distribution for compact embedded systems in addition to the novel interconnect paradigm.
  • Keywords
    field programmable gate arrays; multiprocessor interconnection networks; peripheral interfaces; system buses; time division multiplexing; PCIexpress; analog signals; bus architectures; bus implementation; bus interface circuitry; compact embedded systems; conventional serial buses; data word; digital peripheral interconnect buses; digital signals; field-programmable gate array; intermediate data format; miniature robot; morphing bus; nontime-multiplexed mode; novel interconnect paradigm; parallel buses; peripheral device; physical data channel; processor side; programmable devices; serial data channels; signal lines; unique physical I-O stack; Actuators; Connectors; Field programmable gate arrays; Integrated circuit interconnections; Multiplexing; Sensors; Taxonomy; Bus interface circuitry; bus specification; field-programmable gate array (FPGA); peripheral interconnect;
  • fLanguage
    English
  • Journal_Title
    Components, Packaging and Manufacturing Technology, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    2156-3950
  • Type

    jour

  • DOI
    10.1109/TCPMT.2013.2273663
  • Filename
    6595130