DocumentCode
406864
Title
2.5 GSPS/1 GHz wide band digital receiver
Author
Chen, Chien-In Henry ; George, Kiran ; Wang, Mingzhen ; McCormick, William ; Tsui, James B Y
Author_Institution
Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA
Volume
2
fYear
2003
fDate
2-6 Nov. 2003
Firstpage
1888
Abstract
Today´s very deep submicron IC technology enables high performance analog and digital applications to be integrated on a single IC chip. For this effort, a design of 2.5 giga-sample per second (GSPS) electronic warfare (EW) receiver-on-a-chip (ROC) is presented. For our design, we take advantage of a super-resolution technique to reduce sidelobes and spurs for improving instantaneous dynamic range. A major goal is to produce a low cost, small and lightweight, and low power EW ROC. Our design covers a 1 GHz bandwidth (125 MHz - 1125 MHz), and it correctly processes two simultaneous signals by detecting their frequency, pulse width (PW), and time of arrival (TOA). The single or dual signal, spur free dynamic ranges and two signal instantaneous dynamic ranges of our design are high. The minimum frequency separation of two signals is 10 MHz (one channel width), the maximum amplitude separation of two signals is 18 dB, and the second signal false alarm is less than 1%.
Keywords
broadband networks; digital radio; electronic warfare; integrated circuits; military communication; radio receivers; signal detection; 1 GHz; 10 MHz; 125 to 1125 MHz; 2.5 GHz; digital receiver; electronic warfare; receiver-on-a-chip; single IC chip; spur free dynamic ranges; submicron IC technology; super-resolution technique; Analog integrated circuits; Application specific integrated circuits; Costs; Digital integrated circuits; Dynamic range; Electronic warfare; Frequency; Signal design; Signal resolution; Wideband;
fLanguage
English
Publisher
ieee
Conference_Titel
Industrial Electronics Society, 2003. IECON '03. The 29th Annual Conference of the IEEE
Print_ISBN
0-7803-7906-3
Type
conf
DOI
10.1109/IECON.2003.1280348
Filename
1280348
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