Nanoscale science and technology - a device and engineering perspective

Present-day silicon CMOS has already entered the nanoscale era, with general lithography feature size at 90 nm and minimum gate lengths below 50 nm. Continued device performance improvement is possible only through a combination of device scaling with new device structure and/or new materials. This paper reviews the recent progress in continuing CMOS scaling by introducing new device structures and new materials. Starting from an analysis of the sources of device performance improvements, we present technology options to achieving these performance enhancements.