Title :
A novel 0.8 V BP-DTMOS content addressable memory cell circuit derived from SOI-DTMOS techniques
Author :
Shen, E. ; Kuo, J.B.
Author_Institution :
Waterloo Univ., Ont., Canada
Abstract :
This paper reports a novel 0.8 V BP-DTMOS content addressable memory (CAM) cell circuit derived from SOI DTMOS techniques, implemented in a 0.18 μm bulk CMOS technology. According to experimentally measured results of a test chip, this 0.8 V CAM cell derived from SOI-DTMOS techniques has 1.7 ns tag-compare time, which is 47% faster as compared to the one without using the BP-DTMOS technique.
Keywords :
CAD; CMOS memory circuits; content-addressable storage; integrated circuit testing; silicon-on-insulator; 0.18 micron; 0.8 V; 1.7 ns; BP-dynamic-threshold MOS content addressable memory cell circuit; CMOS technology; SOI-DTMOS; Associative memory; CADCAM; CMOS technology; Circuit testing; Computer aided manufacturing; Low voltage; MOS devices; Random access memory; Very large scale integration; Voltage control;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2003 IEEE Conference on
Print_ISBN :
0-7803-7749-4
DOI :
10.1109/EDSSC.2003.1283523
