Title :
Simultaneous multiple-Vdd scheduling and allocation for partitioned floorplan
Author :
Kang, Dongku ; Johnson, Mark C. ; Roy, Kaushik
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
In this paper we propose a simultaneous scheduling and allocation algorithm for voltage-partitioned multiple-Vdd design. By considering voltage partition during scheduling and allocation, we may place the resources of same voltage in one partition, thereby reducing additional power meshes. Also, the partitioned design reduces the energy dissipation of level converters by reducing cutsize between different-voltage partitions. The proposed algorithm starts from a random solution. Then, it performs scheduling and allocation simultaneously while trying to satisfy both resource and time constraints. By gradually changing the schedule and allocation, the algorithm effectively explores solution spaces to achieve low-power and better partitioning in terms of the supply voltages. Relative to the minimum single voltage design, 36% of energy saving was achieved. Also, improvements for interconnect, level-conversion energy, and voltage clusters were observed.
Keywords :
circuit complexity; circuit layout CAD; data flow graphs; integrated circuit layout; low-power electronics; complexity; data-flow graphs; hill-climbing method; low-power CMOS circuits; minimum single voltage design; multiple-Vdd scheduling; partitioned floorplan; random solution; reduced additional power meshes; simultaneous scheduling and allocation algorithm; Circuits; Clocks; Energy dissipation; Partitioning algorithms; Processor scheduling; Resource management; Scheduling algorithm; Throughput; Time factors; Voltage;
Conference_Titel :
Quality Electronic Design, 2004. Proceedings. 5th International Symposium on
Print_ISBN :
0-7695-2093-6
DOI :
10.1109/ISQED.2004.1283657