DocumentCode :
407571
Title :
Rewiring for watermarking digital circuits
Author :
Khan, M. Moiz ; Tragoudas, Spyros
Author_Institution :
Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA
fYear :
2004
fDate :
2004
Firstpage :
143
Lastpage :
148
Abstract :
A resynthesis method to protect firm cores or circuit netlist representations is presented. The design is protected by embedding a watermark by rewiring the circuit with one or more redundancy addition/removal steps. There is no or negligible area or timing overhead and existing test sets may be presented. We analyze several attack strategies and we experimentally demonstrate that the proof of authorship is guaranteed with very high probability for ISCAS´85 and ITC´99 benchmarks.
Keywords :
automatic test pattern generation; industrial property; logic design; redundancy; watermarking; ATPG-based resynthesis techniques; IP; attack strategies; circuit netlist representations; design protection; digital circuit rewiring; digital circuit watermarking; firm cores; intellectual property; proof of authorship; redundancy addition/removal steps; watermark embedding; Circuit testing; Design optimization; Digital circuits; Hardware design languages; Intellectual property; Protection; Tiles; Time to market; Timing; Watermarking;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design, 2004. Proceedings. 5th International Symposium on
Print_ISBN :
0-7695-2093-6
Type :
conf
DOI :
10.1109/ISQED.2004.1283665
Filename :
1283665
Link To Document :
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