• DocumentCode
    408425
  • Title

    Gate-leakage estimation and minimization in CMOS combinatorial circuits

  • Author

    Guindi, Rafik S.

  • Author_Institution
    Commun. & Electron. Eng., Cairo Univ., Giza, Egypt
  • fYear
    2003
  • fDate
    9-11 Dec. 2003
  • Firstpage
    85
  • Lastpage
    88
  • Abstract
    This work presents a methodology for estimating and minimizing the total amount of gate-tunneling current in CMOS combinatorial circuits. We take advantage of the state-dependency exhibited by the gate-leakage and use signal probabilities to optimize internal circuit interconnections. Results are given for a number of ISCAS-85 benchmark circuits.
  • Keywords
    CMOS logic circuits; combinational circuits; integrated circuit interconnections; leakage currents; logic gates; CMOS combinatorial circuits; benchmark circuits; gate leakage; gate tunneling current; internal circuit interconnections; CMOS logic circuits; CMOS technology; Insulation; Integrated circuit interconnections; Leakage current; Logic gates; MOS devices; MOSFETs; Minimization; Tunneling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microelectronics, 2003. ICM 2003. Proceedings of the 15th International Conference on
  • Print_ISBN
    977-05-2010-1
  • Type

    conf

  • DOI
    10.1109/ICM.2003.1287728
  • Filename
    1287728
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=408425