Implementation of artificial neural networks on on-chip interconnects in VLSI circuits

The advent of the VLSI circuits has brought down the size of the semiconductor devices considerably. As the size decreases the effects of reduced chip dimensions dominates the performance of the circuits. Consequently, the interconnection and packaging related issues are among the main factors that determine the number of circuits that can be integrated on a chip as well as the chip performance. The wiring capacitance and impedance, transmission line phenomenon, cross-talk between wires, simultaneous switching noise and clock skew are the factors that affect the performance of the circuits. The objective of this paper is to optimize on-chip interconnects for crosstalk and propagation delay using artificial neural networks.