A hybrid CSA tree for merged arithmetic architecture of FIR filter

Most hardware optimization schemes for fixed digital filter implementation rely on the use of canonical signed digit filter coefficients to replace the costly multipliers by shifters and adders. This paper further leverages on the optimally encoded coefficients generated by any existing filter coefficient synthesis algorithm by introducing two techniques to increase the performance and reduce the circuit complexity for the direct form FIR filter implementation based on the multiplierless structure. Firstly, merged arithmetic is used to merge the shift and add operations with the accumulation operations. The circuit complexity is greatly reduced in the proposed structure and the latency of the system can be tailored to the required throughput rate by having multiple merged arithmetic blocks if necessary. Secondly, a generalized hybrid adder allocation scheme is developed. The resulting CSA structure achieves a 30% - 40% saving on silicon area compared to those with the traditional Wallace structure, and at the same time the width of the final stage carry propagation adder is shortened which effectively reduces the critical path delay.