Implementation of a reconfigurable architecture

Author

Vejanovski, R. ; Stojcevski, A. ; Singh, J. ; Zayegh, A. ; Faulkner, Michael

Author_Institution

Sch. of Electr. Eng., Victoria Univ., Melbourne, Vic., Australia

Volume

2

fYear

2003

fDate

14-17 Dec. 2003

Firstpage

447

Abstract

Implementation of a reconfigurable architecture for an UTRA-TDD mobile terminal receiver is described. The architecture consists of a variable length digital channel filter and a variable word length pipeline ADC. The lengths depend on in-band and out-of-band power ratios. The architecture is power efficient and only consumes minimum power to meet the signal to noise ratio of the system. An average poker consumption of 13.3 mW has been recorded.

Keywords

3G mobile communication; analogue-digital conversion; application specific integrated circuits; digital filters; digital signal processing chips; low-power electronics; mobile handsets; pipeline processing; reconfigurable architectures; telecommunication computing; time division multiplexing; 13.3 mW; ASIC; DSP; UMTS terrestrial radio access; UTRA-TDD mobile terminal receiver; downlink time division duplex mode; hardware software partitioned; in-band power ratios; out-of-band power ratios; power efficient architecture; reconfigurable architecture implementation; variable length digital channel filter; variable word length pipeline ADC; Application specific integrated circuits; Batteries; Costs; Digital filters; Energy consumption; Finite impulse response filter; Interchannel interference; Mobile communication; Pipelines; Reconfigurable architectures;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on

Print_ISBN

0-7803-8163-7

Type

conf

DOI

10.1109/ICECS.2003.1301818

Filename

1301818