A 68MHz multi-channel all-digital programmable oscillator

Author

Abdollahi, S.R. ; Fakhraie, S.M. ; Kamaeri, M. ; Abdollahi, S.E.

Author_Institution

ECE Dept., Univ. of Tehran, Iran

Volume

2

fYear

2003

fDate

14-17 Dec. 2003

Firstpage

475

Abstract

A 68MHz programmable digitally-controlled oscillator (DCO) core is designed in 0.25 micron CMOS process and its prototype design is mapped on an Altera MAX9400 CPLD. This architecture is suitable for digital wireless transceivers that use different bands for transmit and receive modes, such as GSM and DECT. Linearity and phase noise of the DCO is analyzed. Thermal drift and power supply level sensitivity is characterized. This architecture can be used at higher frequencies by using faster FPGA devices or by implementing it in an advanced deep-submicron CMOS process.

Keywords

CMOS analogue integrated circuits; SPICE; application specific integrated circuits; circuit simulation; digital phase locked loops; field programmable gate arrays; integrated circuit design; transceivers; transfer functions; voltage-controlled oscillators; 68 MHz; ASIC implementation; Altera MAX9400 CPLD; CMOS process; DECT; GSM; HSPICE; Hanning window; digital wireless transceivers; fine-tuning circuits; flexible programmable oscillator; linear transfer function; linearity; multichannel all-digital programmable oscillator; phase noise; power supply level sensitivity; programmable delay cells; prototype design; thermal drift; CMOS process; Frequency; GSM; Linearity; Oscillators; Phase noise; Power supplies; Prototypes; Transceivers; Wireless sensor networks;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on

Print_ISBN

0-7803-8163-7

Type

conf

DOI

10.1109/ICECS.2003.1301825

Filename

1301825