Enhancing performance of iterative heuristics for VLSI netlist partitioning

Author

Sait, Sadiq M. ; El-Maleh, Aimn H. ; Al-Abaji, R.H.

Author_Institution

Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia

Volume

2

fYear

2003

fDate

14-17 Dec. 2003

Firstpage

507

Abstract

In this paper we, present a new heuristic called PowerFM which is a modification of the well-known Fidducia Mattheyeses algorithm for VLSI netlist partitioning. PowerFM considers the minimization of power consumption due to the nets cut. The advantages of using PowerFM as an initial solution generator for other iterative algorithms, in particular Genetic Algorithm (GA) and Tabu Search (TS), for multiobjective optimization is investigated. A series of experiments are conducted on ISCAS-85/89 benchmark circuits to evaluate the efficiency of the PowerFM algorithm. Results suggest that this heuristic would provide a good starting solution for multiobjective optimization using iterative algorithms.

Keywords

VLSI; circuit layout CAD; circuit optimisation; genetic algorithms; integrated circuit layout; iterative methods; logic CAD; logic partitioning; minimisation of switching nets; search problems; ISCAS-85/89 benchmark circuits; PowerFM heuristic; Tabu search; VLSI netlist partitioning; circuit partitioning; cut-set cost function; genetic algorithm; initial solution generator; iterative heuristics; min-cut gain calculation; multiobjective optimization; power consumption minimization; switching probabilities; timing performance; Circuits; Clocks; Energy consumption; Frequency; Iterative algorithms; Minerals; Partitioning algorithms; Petroleum; Power engineering computing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on

Print_ISBN

0-7803-8163-7

Type

conf

DOI

10.1109/ICECS.2003.1301833

Filename

1301833