• DocumentCode
    412987
  • Title

    Efficient modulo 2n+1 tree multipliers for diminished-1 operands

  • Author

    Efstathiou, C. ; Vergos, H.T. ; Dimitrakopoulos, G. ; Nikolos, D.

  • Author_Institution
    Dept. of Informatics, TEI of Athens, Greece
  • Volume
    1
  • fYear
    2003
  • fDate
    14-17 Dec. 2003
  • Firstpage
    200
  • Abstract
    In this work we propose a new method for designing modulo 2n+l multipliers for diminished-1 operands. Our multipliers compared to the already known tree architecture offer enhanced operation speed for the majority of n values, with similar area complexities. They also have very regular structure, and can be pipelined at the full-adder level.
  • Keywords
    adders; pipeline arithmetic; residue number systems; tree data structures; Wallace tree; diminished-1 operands; efficient modulo 2n+1 tree multipliers; enhanced operation speed; full-adder level pipelining; low hardware cost; regular structure; residue number system; unit-gate model; Arithmetic; Bismuth; Costs; Delay; Design methodology; Hardware; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on
  • Print_ISBN
    0-7803-8163-7
  • Type

    conf

  • DOI
    10.1109/ICECS.2003.1302011
  • Filename
    1302011
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=412987