• DocumentCode
    413047
  • Title

    Translating submachine locality into locality of reference

  • Author

    FANTOZZI, Carlo ; Pietracaprina, Andrea ; Pucci, Geppino

  • Author_Institution
    Dept. of Inf. Eng., Padova Univ., Italy
  • fYear
    2004
  • fDate
    26-30 April 2004
  • Firstpage
    34
  • Abstract
    Summary form only given. The design of algorithms exhibiting a high degree of temporal and spatial locality of reference is crucial to attain good performance on current and foreseeable computing systems featuring ever deeper memory hierarchies. Previous work has demonstrated that task parallelism can be efficiently transformed into locality of reference in two-level hierarchies. Recently, we moved a step forward and showed how the more structured type of parallelism exposed by submachine locality can be efficiently turned into temporal locality on arbitrarily deep hierarchies. We complete and extend the above result by encompassing also spatial locality. Specifically, we present a scheme to simulate parallel algorithms designed for the decomposable BSP (a BSP variant which captures submachine locality) on the hierarchical memory model with block transfer. The simulation yields good hierarchy-conscious sequential algorithms from parallel ones, and provides evidence of the strict relation between submachine locality in parallel computation and locality of reference (both temporal and spatial) in the hierarchical memory setting.
  • Keywords
    parallel algorithms; storage management; temporal databases; visual databases; block transfer; decomposable BSP; deeper memory hierarchies; foreseeable computing systems; hierarchical memory model; hierarchical memory setting; hierarchy-conscious sequential algorithms; parallel algorithm simulation; parallel computation; spatial reference locality degree; submachine locality; submachine locality transfer; task parallelism; temporal reference locality degree; two-level hierarchies; Algorithm design and analysis; Computational modeling; Concurrent computing; Costs; Design engineering; Hidden Markov models; Parallel algorithms; Parallel processing; Phase change random access memory; Random access memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International
  • Print_ISBN
    0-7695-2132-0
  • Type

    conf

  • DOI
    10.1109/IPDPS.2004.1302947
  • Filename
    1302947