Gate-last MISFET structures and process for high-k and metal gate MISFETs characterization

We propose new test device structures, gate-last-formed structures, which are suitable for fundamental study of high-k gate insulator or metal gate electrode MISFETs. The gate insulator and electrode are formed after local interconnect pads connected with source and drain. The gate electrode is formed in a trench by dry and wet etching techniques and is non-self-aligned to the source and drain. The wet etching restricts damage formation on the exposed Si surface underneath the trench. This structure can provide methods both for fundamental evaluation and for material selection of new gate stack materials by investigation of MISFET characteristics. This is achieved with short TAT and avoiding contamination penalty to a fab.