An array cell transistor test structure for the leakage current analysis of stacked capacitor DRAMs with diagonal cell scheme

Author

Kim, Young Pil ; Jin, Beom Jun ; Yeo, Gi-Sung ; Lee, Sun-Ghil ; Choi, Siyoung ; Chung, Uin ; Moon, Joo Tae ; Kim, Sang U.

Author_Institution

Semicond. R&D Center, Samsung Electron. Co. Ltd, Kyonggi-do, South Korea

fYear

2004

fDate

22-25 March 2004

Firstpage

139

Lastpage

142

Abstract

A new test structure for a stacked capacitor DRAM cell transistors with a diagonal active-area was developed to analyze the leakage current characteristics of the cell transistors. The leakage current components of the low power DRAMs with different retention fail distributions was investigated in detail using the test structure, and the important aspect of the sub-threshold leakage component was discussed for below 0.11 μm DRAM cell transistors.

Keywords

DRAM chips; integrated circuit measurement; integrated circuit testing; leakage currents; array cell transistor test structure; bit-line contact; diagonal cell scheme; gate-induced drain leakage; leakage current analysis; low power DRAM; retention fail distributions; self-aligned contact; stacked capacitor DRAM; subthreshold leakage component; Capacitors; Current measurement; Electronic equipment testing; Failure analysis; Insulation; Leakage current; Moon; Random access memory; Research and development; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2004. Proceedings. ICMTS '04. The International Conference on

Print_ISBN

0-7803-8262-5

Type

conf

DOI

10.1109/ICMTS.2004.1309467

Filename

1309467