Experimental measurements and extraction of the silicide/silicon interface resistance for designing high performance MOS transistor

The interface resistance between cobalt salicide and silicon has been investigated from the viewpoint of its effects on the performance of dual gate CMOSFETs. With a very simple structure, including some salicidation-blocking regions at the cobalt-salicided silicon resistor bar pattern, the interface resistances could be extracted for various process conditions. The performance of the transistor for each process condition was well correlated with the extracted interface resistance. From the relationship between the interface resistance and the transistor performance, we could optimise the cobalt salicidation process for high performance MOSFETs.