Accuracy improvement of the "Single Pattern Driver" method for the characterization of interconnect capacitance in the context of nanometer technology development

Author

Brut, H. ; Martin, S. ; Froment, B.

Author_Institution

STMicroelectronics, Crolles, France

fYear

2004

fDate

22-25 March 2004

Firstpage

303

Lastpage

308

Abstract

Characterization, modelling and monitoring of interconnect capacitance are of first interest for CMOS and BiCMOS technology development, especially for circuit delay evaluation. An improvement of the Single Pattern Driver method is proposed in this paper to take into account MOST intrinsic and diode leakages which can introduce errors of the order of few hundred aF in advanced nanometer technologies. The accuracy is hugely improved and reaches now 10aF.

Keywords

BiCMOS integrated circuits; CMOS integrated circuits; capacitance measurement; integrated circuit interconnections; integrated circuit measurement; integrated circuit modelling; integrated circuit testing; leakage currents; nanoelectronics; BiCMOS technology; CMOS technology; accuracy improvement; circuit delay evaluation; diode leakages; interconnect capacitance; interconnect modelling; intrinsic leakages; leakage currents; nanometer technology development; single pattern driver method; CMOS technology; Capacitance measurement; Circuit testing; Current measurement; Driver circuits; Integrated circuit interconnections; MOS devices; Monitoring; Parasitic capacitance; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2004. Proceedings. ICMTS '04. The International Conference on

Print_ISBN

0-7803-8262-5

Type

conf

DOI

10.1109/ICMTS.2004.1309501

Filename

1309501