Design methodology for multiple domain power distribution systems

High-speed digital devices require multiple voltage and frequency domains to accommodate the core logic and the input/output (I/O) circuitry for multiple interfaces. In addition, some of these interfaces are programmable to various speeds and signaling modes and they require multiple power supply voltages. These requirements create complex power delivery and signal distribution solutions. This paper proposes a design methodology for fast transient point of load (POL) power distribution architectures for microprocessors and fast switching logic. This paper presents an efficient power distribution system (PDS) design methodology that models the load, its point of load power converter, and the transporting system so that the entire system can be efficiently implemented in circuit simulation as a complete integrated setup for design optimization. Models for the voltage regulator module (VRM) and its transient response and stability, the active load with multiple power supply domains, and the power planes are discussed in detail. System voltage noise margin budgeting is also emphasized.