Power delivery validation methodology and analysis for network processors

The rapid growth in power consumption has created numerous issues for high performance processors. In addition to the increase in average power, the dynamic power fluctuation (di/dt) injects substantial noise in the processor power delivery network. These transients tend to expose the voltage-sensitive critical paths, and therefore the higher specified product frequency is limited by the lowest voltage transient point. To contain the noise on the voltage rail to within acceptable limits, the common approach is to place decoupling capacitors between the power and ground planes at different stages (voltage regulator, motherboard, package, die) to keep the power delivery network impedance to within a certain target. A good understanding of the behavioral model of the capacitors and the dynamic power fluctuation is necessary in order to accurately predict the noise on the processor voltage rail. This paper provides a validation methodology for measuring and analyzing the voltage droops in the power distribution network and discusses the mechanisms that trigger the different voltage droops in the power delivery network.